中美不睦，美國高科技晶片巨頭的大批中國籍員工悲催躺槍

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“中美貿易戰”、“美國晶片商集體斷供華為”這樣的話題最近不斷承包我們的新聞頭條，身在美國的中國留學生、移民群體每天不僅要關注中美兩國的宏觀大事件動態，更要留心可能會影響到自己日常學習、工作、生活的規定的更改，這裡集體心疼我們自己一分鐘…

這樣細枝末節的影響存在在很多方面

⬇️

有人覺得

申請赴美簽證的難度提高了

有人覺得

移民申請的審批速度變慢了

有人覺得

美國僱主開放給外籍員工的工作機會少了

我們多麼希望這些體驗只是個人的主觀感受、並非大勢所趨，但是很遺憾，這一切都並非是少數個例。

當前藉著“華為、晶片”話題的熱度，美國媒體紛紛解析對行業、企業、國家經濟的影響，而《華爾街日報》特意調查了一下這些爭端對美國晶片產業的中國籍員工有什麼影響呢？

調查之後記者發現，原來在美國晶片製造產業填補著大量人才空缺的中國籍僱員成為了“犧牲品”，他們在美國晶片製造產業的職業生涯遭受到前所未有的衝擊。

美國晶片製造巨頭的困局：缺人！

美國晶片製造產業的巨頭公司從去年開始，強烈地感受到僱傭中國籍高階工程師越來越艱難，這些公司包括大家耳熟能詳的英特爾、高通、格芯(Globalfoundries)等。

過去很長一段時間這些高科技公司招聘了很多中國籍僱員作為高階工程師，尷尬的是一旦出現這類技術人才缺口，這些企業不能在美國本土員工中找到同質同量的人才補上。但美國政府正在從政策層面為這些急需技術人才的美國僱主製造麻煩，在他們僱傭中國籍人才的通道上頻頻設限。

從去年開始這個問題已經為美國晶片製造巨頭們豁開了成百上千的用人口子，他們不僅很難在美國本土招聘到心儀的中國籍人才，連從中國分公司調配技術人員赴美也難上加難。

這種艱難不是找不到合適的人才，而是即使發了offer，美國政府往往會因為該員工的中國國籍而設限不予批准。

外國僱員所需的特別許可證

大家都知道外國人在美國合法工作都需要有僱主出面申請H-1B、L-1這樣的工作簽證，除此以外如果該僱主屬於敏感技術行業，在一些關鍵研發、技術崗位僱傭外國人時還要申請一種特別許可證——視同出口許可證(deemed-export licenses)。

官方解釋視同出口許可證，版權屬於原作者

視同出口許可證，是美國出口管制體系的重要環節之一，目的是為了限制向外國轉讓敏感技術以確保美國的技術安全、軍事領先優勢等。中國、伊朗、俄羅斯等國一直都是美國視同出口管制的重點物件。

所有持非移民簽證居留在美國境內的外國人，都是視同出口限制的潛在管理物件。只有三種外國人不受管制，分別是綠卡持有者、被授予美國公民身份者、根據法律被認定為“在美國受保護者”(例如政治流亡者或政治庇護者)。

如果有美國公司、機構想僱傭外國留學生、高技術工人、科學家，或者想邀請外國人來參觀訪問，而這其中可能會涉及、接觸美國政府明確列出的受控清單上的知識、技術時，這些美國公司、機構必須向主管機構提出視同出口許可證申請。

主管部門收到申請後會進行材料審查，根據所涉及外國人的國籍、所涉及機構或行業的性質、技術可能會落入美國競爭對手手中的風險等進行判定。一般發放一次視同出口許可證的有效期為兩年，到期後可以再向相關部門申請更換。

中國籍員工受影響最大

像英特爾、高通這樣的晶片製造商因為涉及到半導體、電信系統、加密技術等敏感科技領域，必須為公司現有和想要招聘的外籍僱員申請特殊許可證。

以前為外籍員工申請一份視同出口許可證只需要幾周的審理時間，現在等待6-8個月很常見。中國留學生的交流論壇帖裡，有同學抱怨自己的申請已經等了一年+了。

官方對於視同出口許可證審理嚴重拖延的解釋是：“商務部需要與包括國務院、國土安全部、國防部、能源部門等眾多政府機構合作，為了謹慎考量每一份申請存在的風險，審理部門需要要求申請公司、機構提供更多、更充分的資訊。” 私認為這裡提到的企業被要求提供“更多更充分資訊”等同於他們被RFE了…

這種變化是從2018年逐漸明顯的，中美貿易爭端、美國擔心核心技術流失、各種版本層出不窮的“間諜說”都對視同出口許可證審批產生了很大影響。

這種變化在美國科技製造產業很普遍，但對晶片製造商來說更加麻煩，因為能夠從事高階技術工程的人才非常有限。根據美國商務部的資料，從2013年到2017年，視同出口許可證申請中中國公民佔總數的60%以上，而最常見的涉及行業就是晶片、電信技術。

截圖來源於wsj.com，版權屬於原作者

業內人士表示，雖然相關美國公司並未停止招聘中國籍僱員，但特殊許可證審批的過度拖延導致僱主失去了很多他們當初選定的優秀候選人，也嚴重影響了公司專案程序管理以及崗位分配製度。

這樣的變化與美國當局拖延H-1B、L-1等工作簽證的稽核發放的套路完全一致，透過拖延審理時間、製造稽核障礙，迫使美國僱主從僱傭外籍員工的源頭上“知難而退”。

晶片屆的小夥伴，如果在美國公司受挫，不如嘗試下對華人更為友好的中資公司。WE Career獨家內推渠道，歡迎投遞簡歷～

招聘公司

The Company is an IDM memory solutions company which designs, manufactures and sells memory products and solutions for a broad range of applications including Mobile Devices, Computing, Data centers and Consumer Electronics for customers around the world.

3D NAND Memory Engineer

Location

San Jose, CA

The candidate should be able to synthesize the requirements from various sources, including the management directions and lead actions through the team in a systematic fashion. The candidate should have the technical cognizance to absorb the information, set the right direction and coach the team to success. The candidate must have 3 years and above related working experiences.

Job Description

Design control circuits for memory core operations, provide layout guidelines.
Perform power/ground network analysis.
Hand-on silicon debugging and characterization.
Have good understanding of Solid-State device physics.
Comfortable with IC tools such as Cadence analog design environment, HSPICE/FINESIM, UNIX.

NAND Logic Design Engineer

Location

San Jose, CA

This Position is part of 3D NAND logic design team.

Candidate will be a technical individual contributor in Logic design include on-chip controller, NAND interface, Functional Block and FW development.

Primary Responsibilities

Solid knowledge of modeling and designing of VLSI circuits and systems.
Architecture development and product definition, system integration and full-chip and block-level validation plan and execution.
Design concept of combinational and sequential logic and Register transfer level digital circuit design with Verilog/ VHDL.
RTL design and implementation of the controller HW, Development of Firmware for NAND operations like Program, Read, Erase.
Logic Synthesis, P&R and Full chip Timing Closure : Analysis knowledge and Experience.
Hands-on silicon debugging/evaluation experience.
Work closely with other teams to follow up with all phases of design from conceptual design to production support efficiently.

Prefer Skills

MS or PhD degree in Electrical Engineering, Computer Science, Physics, Mathematics or equivalent disciplines.
Industrial experience in Non-Volatile Memory(NAND) Design is Particular and Dedicated FW Algorithms.
Experience of the Entire Digital Design Flow, from the Spec all the way to the Physical Design.
Understanding of semiconductor physics on NAND device and MOSFET transistors.
Knowledge of TCL, PERL or Python is a plus.
Experience with mixed-signal design and validation is a plus.
Knowledge and Experience with transistor level simulators such as Spice, XA, Finesim, Ultrasim etc. is a plus.
Experience with UVM and test bench development is a plus.

NAND Verification Engineer

Location

San Jose, CA

Primamry Responsibilities

Full-chip functional verification on NAND flash design projects.
Coverage driven test bench development in SystemVerilog/UVM.
Support of design verification methodology enhancements.
Technical support to verification team members in China.

Qualifications

Minimum two years of industrial experience in logic design verification projects.
NAND flash memory or related design verification experience is strongly preferred.
Must have solid knowledge and experience of test bench development in SystemVerilog and UVM.
Experience with scripting language such as PERL/Python is desired.
Fluent in both Mandarin and English is preferred.
MS degree in Electrical/Computer Engineering or equivalent

申請方式

傳送簡歷至 [email protected]

標題註明“職位+姓名“

招聘公司

成立於矽谷，該公司是一家以AI晶片為核心技術的創業公司，擁有從 3D 感測器、特定領域 AI 晶片到軟體的全棧解決方案，目前在矽谷和中國深圳均有團隊。目前國內開放以下職位：

RTL Designer

Location

Santa Clara, CA

Shenzhen, China

Primary Responsibilities

Design RTL for our CPU-centric Machine Learning ASIC chip.
Optimize timing and power consumption.
Support functionality debug in simulation and emulation.
Write timing/power constraint for the design

Qualifications： Must

MS or PhD degree in Electrical Engineering, Computer Science, Physics, Mathematics or equivalent disciplines.
MS with > 2 years of industrial experience; more experiences and capability will correspond to higher job levels.
Excellent RTL design skills with System Verilog.
Good scripting skills with Python/Perl/Tcl.
Solid understanding of low power optimization.
Proficient communication in English – both orally and in writing form.
Self-driven, result-oriented; able to multi-task and determine priorities.
A proven fast learner and a team player.

Preferred

Knowledge and experience with RISC-V ISA is highly desired.
Knowledge about CPU architecture and memory hierarchy.
Experience of working with foreign coworkers and remote teams is a plus.

Design Verification Engineer

Location

Santa Clara, CA

Shenzhen, China

Primamry Responsibilities

Verifying the design, architecture and micro-architecture using advanced verification methodologies.
Defining the verification scope and contributing to the development of the verification infrastructure.
Collaborating with architects, designers, and software engineers across sites to accomplish verification targets

Qualifications

A BS degree in Electrical Engineering, Computer Science or other equivalent disciplines with > 5 years of relevant work or research experience, or a MS degree of the above areas with > 2 years of similar experience.
Experience in verification using random stimulus along with functional coverage and assertion-based verification methodologies.
Fluency in Object Oriented Programming with C++ and/or SystemVerilog.
Exposure to design and verification tools (VCS or equivalent simulation tools, debug tools like Debussy, GDB), and methodologies (UVM or equivalent)
Passionate about debugging and comprehensive problem-solving skills.
High proficiency in English – both orally and in writing form.
Excellent communication skills; both articulate and a good listener.
Self-driven, result-oriented; able to multi-task and determine priorities.
A proven fast learner and a team player.
Experience of working with foreign coworkers and remote teams is a plus.